The Xilinx Adaptive Compute PhD school in association with ETH Zurich HACC, Developing accelerators using FPGAs was held virtually during the days 11-15th January 2021.
The school offered students an opportunity to learn about FPGA design and recent technology developments, and gain hands-on experience creating FPGA accelerators with Xilinx software.
An introduction to FPGA and Zynq technology was covered including the PYNQ framework, along with some hands-on tutorials and examples on local hardware (provided by the Xilinx University Program to each attendee). The Xilinx Vitis software development environment for designing FPGA accelerators was introduced.
Participants devised and built their own custom accelerators targeting Alveo and AWS F1 instances. Students followed the guidance of the instructors to build custom designs from available open source libraries or to create their own custom accelerator design.
The school also included invited presentations from speakers at ETH Zurich and Xilinx on relevant topics, including an overview of the HACC program and the HACC at ETH Zurich.
| FPGAs on cloud and datacenters; Prof. Gustavo Alonso (ETH Zurich) | VNx: XUP Vitis UDP Network Example for Alveo; Dr. Mario Ruiz (XUP) |
| EasyNet: 100Gbps Network for HLS; Zhenhao He (ETH Zurich) | FPGA Accelerated Computing, Kumar Deepak (Xilinx Data Center Group) |
| Data-Centric Parallel Programming; Johannes de Fine Licht (ETH Zurich) | |
The Vitis and PYNQ prerecorded presentation and slides can be found in the XUP Compute Acceleration presentations
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